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Objectives

  • A retimer chip for a 100Gbps QSFP optic transceiver module will be designed, validated, taped-out and made production ready.

Deliverables

  • Custom designed production ready Retimer chips for realizing IEEE 802.3ba compliant 100Gbps transceivers

  • Stretch goal : 200Gbps

Co-Principal Investigator:

Kishen Amarnath

Principal Engineer

Signalchip Innovations

Principal Investigator:

Nikhik BG

Design director

Signalchip Innovations

WP01

Development of retimer chip for QSFP transceiver

Organization:

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