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Objectives
To demonstrate electronic retimer ICs on the 28 nm CMOS technology platform, that enables >100 Gb/s and/or >200Gb/s per fiber data transmission, meeting jitter specifications specified in the IEEE 802.3 bs standard (Table 120D-7).
To co-package one or more ASICs designed in-house with COTS TOSA/ROSA.
Deliverables
Board-level demo using COTS optics and in-house designed ASICs for PAM4 data transmission.
Optical testing of the transmit signals viz. eye diagrams, interoperability with a reference receiver. Receiver BER testing using a break-out board, a reference transceiver, and a BERT.
Stress testing.
Co-Principal Investigator:
Principal Investigator:
WP03
Hybrid integration for high-speed transceiver
Organization:
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